1. Field of the Invention
The present invention relates to a semiconductor device and a data processing system including the same, and more particularly relates to a semiconductor device that can relieve sporadically occurring bit defects and a data processing system including the semiconductor device.
2. Description of Related Art
A memory capacity of semiconductor memory devices, represented by a DRAM (Dynamic Random Access Memory), is increasing in recent years due to progress in downsizing techniques. However, advancement in downsizing has given rise to increasing numbers of defective memory cells per chip. When a memory cell is defective, it is replaced by a redundant memory cell, and the defective address is relieved.
Generally, a defective address is stored in a fuse circuit including a plurality of program fuses. When an access request is made with respect to a defective address, a control is performed in the fuse circuit whereby a redundant memory cell is accessed instead of the defective memory cell. Such defective addresses are detected during a screening test performed at a wafer state. The program fuse is cut by irradiation of a laser beam, according to the detected defective address.
However, even after the address replacement described above, there may be sporadic occurrences of defective bits due to heat stress or the like during packaging. If the defective bits are found after packaging, address replacement by irradiation of the laser beam can no longer be performed, due to which the product will have to be regarded as defective.
To provide a solution to the above problem, a method has been proposed whereby, in addition to address replacement by irradiation of a laser beam, there is provided a defect relief circuit that can relieve a small number of defective bits found after packaging. In this method, instead of a fuse circuit that requires irradiation of the laser beam, a non-volatile storage circuit that is writable electrically is used as a storage circuit for storing defective addresses. A so-called “anti-fuse circuit” in which dielectric breakdown of an oxidized film is employed is used as such a memory circuit.
Because the number of defective bits found after packaging is very few compared to the number of defective bits found during a screening test, it is preferable that replacement is performed in units of bits instead of in units of word lines or bit lines. Japanese Patent Application Laid-open Nos. 2002-298596, 2008-71407, 2004-158069, and 2006-268970 describe such a semiconductor device that can relieve sporadic bit defects.
A semiconductor memory device described in Japanese Patent Application Laid-open No. 2002-298596 is a DRAM in which relief memory elements constituted by SRAM cells are placed in a sense amplifier array of a memory cell array to relieve sporadic bit defects.
A semiconductor memory device described in Japanese Patent Application Laid-open No. 2008-71407 is also a DRAM in which relief memory elements are connected to an output terminal of a read amplifier and an input terminal of a write amplifier to relieve sporadic bit defects.
In the semiconductor memory device described in Japanese Patent Application Laid-open No. 2008-71407, a relief circuit is placed at a previous stage to an input/output circuit (a FIFO circuit) that is connected to an external data terminal and in parallel to a main amplifier (150) that reads data from a regular memory cell (110) (FIG. 1). Furthermore, the relief circuit is placed in parallel to a write amplifier WB that writes the data to the regular memory cell (110) (FIG. 3).
In Japanese Patent Application Laid-open No. 2004-158069, there is described an arrangement whereby a relief circuit is placed within a LOGIC macro located outside of a DRAM macro (FIG. 2). Furthermore, the relief circuit is placed in parallel, via a selector, to an input/output bus (MUXOUT) that connects the DRAM macro and the LOGIC macro (FIG. 3).
In Japanese Patent Application Laid-open No. 2006-268970, there is described an arrangement whereby a first relief bit register is placed in parallel to a first read/write amplifier via a read/write bus that is connected to a DQ input/output buffer circuit.
However, in the semiconductor memory device described in Japanese Patent Application Laid-open No. 2002-298596, because the relief memory elements are placed in the sense amplifier array, it is necessary that a line and space value (L/S) of transistors, wirings, and contacts that constitute the relief memory elements is identical, respectively, to a line and space value (L/S) of transistors, wirings, and contacts that constitute the sense amplifiers, to prevent an area of the memory cell array from increasing. This can lead to an increase in the possibility of a defect occurring in the relief memory element itself. Redundant I/O circuits can be used to relieve the defect in the relief memory element. However, it is not realistic to have a defect occurring in the circuit itself that is introduced to relieve sporadic bit defects, and then having to increase the number of I/O bus to relieve the defect.
Furthermore, in the semiconductor memory device described in Japanese Patent Application Laid-open No. 2002-298596, because the relief memory elements are placed inside the memory cell array, a distance between the main amplifier (a circuit including a read amplifier and a write amplifier) and the relief memory elements can increase largely depending on a position of a memory block. Moreover, a distance of each of the relief memory elements dispersed throughout the memory block from the main amplifier greatly differs from that of the other relief memory elements. As a result, a read margin and a write margin of the main amplifier for each relief memory element differs greatly, making it necessary to vary operation timings of the main amplifier and the relief memory elements according to the position of the memory block. This makes controlling very complicated.
Furthermore, in the semiconductor memory device described in Japanese Patent Application Laid-open No. 2002-298596, when the sense amplifier and the main amplifier are connected by hierarchized data buses (for example, lower local I/O lines and upper main I/O lines) to take care of the greatly increased distances between the main amplifier and the relief memory elements, contact resistances and the like among multi-layer hierarchy degrade a time constant of the hierarchized data buses having large parasitic capacitances. This leads to a prominent difference in access margins that differ according to the position of the memory block.
Meanwhile, in the semiconductor memory device described in Japanese Patent Application Laid-open No. 2008-71407, the relief memory elements are connected to the output terminals of the read amplifiers and the input terminals of the write amplifiers. Therefore, it is necessary to connect a large number of elements to the relief memory elements, and this makes controlling complicated.